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‧Keysight U4431A MIPITM M-PHY 協議分析儀

Keysight U4431A MIPITM M-PHY 協議分析儀

‧ 產品規格與說明

Keysight U4431A MIPITM M-PHY 協議分析儀

查閱技術規格書:
http://literature.cdn.keysight.com/litweb/pdf/5991-2544EN.pdf?id=2354005


Deep insight to help you win the race to M-PHY

The MIPI™ M-PHY standards are the backbone of next-generation
mobile computing designs.Because these designs are replacing desktop
PCs in many applications,these architectures are much faster
and more complex than in the past.

Mobile designers are adding multiple high-speed busses into their
designs to manage multiple high-resolution cameras, high-speed peripherals,
advanced graphics adapters, and massive memory buffers. This increasing demand
for bandwidth has driven the expansion of the M-PHY specification to include four-lane,
6.0-Gbs options. The U4431A offers up to 16 GB of analysis memory on each lane,
allowing designers to capture tens of seconds of system traffic, even at these high speeds.

In addition, the Keysight U4431A offers “Raw Mode,” a feature that lets designers
see the time-correlated 8b/10b data that underlies each protocol.
These states can be displayed as a waveform or listing,
providing insight into how a packet is formed at the physical layer.

This visibility extends throughout the M-PHY protocol stack,
allowing error detection from the physical layer
to the link and from the transport layers to the high-level application layer.
These views allow engineers to unravel data as it travels
throughout the entire transmission process.

The U4431A also offers powerful tools to isolate and unravel specific events on the bus.
Real-time triggers allow the detection of errors at each layer of the protocol,
filters focus analytic tools on specific types of traffic, and traffic overviews
and measurement markers help designers understand traffic
from entire bursts to nanosecond-resolution detail.

The modular AXIe blade form of the U4431A allows users
to analyze multiple M-PHY busses simultaneously.
These M-PHY busses can be time-correlated with MIPI D-PHY CSI-2 and DSI-1,
PCIe, DDR and HDMI busses—or even generic high-speed logic analyzer modules.
Designers can purchase as many lanes and as much memory
and protocol support as they need today,and upgrade in the future.

 

主要技術規格 

Power to meet the needs of today’s and tomorrow’s designs
• Up to gear 3 HS data rates
• Up to 16 GB trace depth
• Up to 4 data lanes

Complete insight into complex designs
• Track multiple M-PHY busses from the PHY to the application layer
• Raw Mode 8b/10b data views
• Infiniium Oscilloscope integration
• Powerful interface that allows unlimited customization of system views


Powerful triggers
• N-way if/then/else trigger branching with AND/OR logic
• Over 50 triggering macros
• PHY and protocol error triggers
• Event counters, flags, and timers


Flexible probing
• U4433A high-Z flying leads (connects to N5426A ZIF tips)
• U4432A low-Z SMA interface